1. Field of the Invention
This invention relates to integrated circuit structures. More particularly, this invention relates to a highly planarized integrated circuit structure containing one or more MOS devices and a method of constructing the structure.
2. Description of the Prior Art
The use of MOS devices, in preference to bipolar devices, usually occurs when either the low power consumption or high density characteristics of MOS devices are needed or desired. However, an MOS device is usually constructed in a non planarized fashion with steps created when making contact with the source and drain regions which are lower than the gate region. Furthermore, despite the high density of the MOS devices,, the gate contact usually occupies a large area due to the need to make the contact in a position offset to the gate region because of alignment problems.
Furthermore, in the construction of MOS devices, the source and drain junctions may be formed too deep causing the junctions to sometimes extend under the gate region causing overlap capacitance which degrades the performance of the device. The extension of the junction under the gate may be caused by forming the junction too deeply in the substrate. This can also cause the depletion region to extend sideways into the channel causing a short channel effect which further degrades the performance and functionality as well as long term reliability. If the source and drain regions can be formed as shallow junctions, which do not extend laterally, e.g., beneath the gate, the junction capacitance may also be lowered because of the reduction in the junction area.
It would, therefore, be very desirable to be able to construct an integrated circuit structure comprising one or more MOS devices on a substrate in a manner which would address the problems discussed above including the construction of a highly planarized integrated circuit structure incorporating one or more of such devices therein.